Japanese Patent Application Publication No. 2008-135522 (hereinafter, referred to as Patent Literature 1) discloses an insulated gate type semiconductor device having a device region in which a MOS structure is formed and an outer periphery region around the device region. In the device region, a plurality of gate trenches are formed, and in each gate trench, a gate insulating film and a gate electrode are formed. In a range exposed to a bottom surface of the gate trench, a p-type bottom surface surrounding region (hereinafter, referred to as a device portion bottom surface surrounding region) is formed. In the outer periphery region, a plurality of trenches is formed so as to surround the device region, and an insulating layer fills each trench. In a range exposed to a bottom surface of each trench in the outer periphery region, a p-type bottom surface surrounding region (hereinafter, referred to as an outer periphery bottom surface surrounding region) is formed. When a MOSFET turns off, in the device region, a depletion layer expands from the device portion bottom surface surrounding region into a drift region. Thus, depletion of the drift region in the device region is promoted. In addition, in the outer periphery region, a depletion layer expands from the outer periphery bottom surface surrounding region into the drift region. Thus, depletion of the drift region in the outer periphery region is promoted. Therefore, the withstand voltage of the insulated gate type semiconductor device is improved.